(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to improve adhesion between copper and the overlying dielectric in the Damascene process.
(2) Description of the Prior Art
The present invention relates to the creation of copper conductive lines and vias that provide the interconnection of integrated circuits in semiconductor devices and/or the interconnections in a multilayer substrate on which semiconductor device(s) are mounted. The present invention specifically relates to the fabrication of conductive lines and vias by a process known as damascene.
The damascene process is used for a number of applications. The most commonly applied process is first metal or local interconnects. Some early damascene structures have been achieved using Reactive Ion Etching (RIE) but Chemical Mechanical Planarization (CMP) is used exclusively today. Metal interconnects using damascene of aluminum are also explored.
In fabricating very and ultra-large-scale-integration (VLSI and ULSI) circuits with the dual damascene process, an insulating or dielectric material, such as silicon oxide, of a semiconductor device is patterned with several thousand openings for the conductive lines and vias. These openings are filled at the same time with metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel conductive lines of metal, such as copper, in the insulating layers, such as polyimide, of multi-layer substrates on which semiconductor devices are mounted.
Damascene therefore is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings are also formed. In the standard dual damascene process, the insulating layer is coated with a photoresist which is exposed through a first mask with an image pattern of the via openings, the pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through a second mask with an image pattern of the conductive line openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete,, both the vias and line openings are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although this standard damascene process offers advantages over other processes for forming interconnections, it has a number or disadvantages. It requires two masking steps to form the pattern, first for the vias and subsequently for the conductive lines. Furthermore, the edges of the via openings in the lower half of the insulating layer, after the second etching, are poorly defined because of the two etchings. In addition, since alignment of the two masks is critical in order for the pattern for the conductive lines to be over the pattern of the vias, a relatively large tolerance is provided and the vias do not extend the full width of the conductive line.
As dimensions of IC devices within advanced IC's have continued to decrease, so also have the dimensions of conductors and interconnection elements, which connect and interconnect those integrated circuit devices. First level interconnect wires have been traditionally formed using aluminum or aluminum alloys. First level metal interconnect vias have typically been formed using tungsten. In the micron and sub-micron device feature environment, it is increasingly important for conductor and interconnection elements within IC's to have a high level of conductivity while at the same time showing limited susceptibility to degradative phenomenon such as electromigration. In order to simultaneously provide the desired high level of electrical conductivity and low electromigration susceptibility of conductor and interconnection elements within advanced IC's, the use of copper is gaining wider acceptance in these applications. The use of copper and copper metal alloys in these applications is becoming more sophisticated while the effects of various processing conditions and processing applications is becoming better understood.
The application of copper in creating interconnecting lines and vias suffers from a number of disadvantages, including formation of undesirable inter-metallic alloys and/or recombination centers in other parts of the integrated circuit. and they often have low diffusion rates. Copper has the additional disadvantage of being readily oxidized at relatively low temperatures. Copper does however offer the advantage of low cost and ease of processing so that the prior and current art has tended to concentrate on finding ways to overcome these limitations. One of the most difficult problems encountered in processing copper is its susceptibility to oxidation. This severely restricts the use of conventional photoresist processing when patterning copper because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash. Several solutions to the above problem associated with copper processing have been proposed in the prior art. Hoshino (U.S. Pat. No. 4,910,169, dated March 1990) teaches the use of low temperature deposition techniques such as RF sputtering, for coating copper layers with materials such as silicon oxide, silicon nitride, and phosphosilicate glass.
Copper, when used as an interconnect material, has a relatively large diffusion coefficient into silicon dioxide and silicon. Copper from an interconnect may therefore diffuse into the silicon dioxide layer causing the dielectric to be conductive and also decreasing the dielectric strength of the silicon dioxide layer. For this reason, copper interconnects require to be encapsulated by at least one diffusion barrier to prevent the indicated diffusion of the copper into the dielectric layer. Silicon nitride can be used for this diffusion layer. Because silicon nitride has a high dielectric constant compared with silicon dioxide, this diffusion layer increases the capacitance between the interconnect and the substrate thereby having a negative effect on device performance.
In the damascene process, good adhesion between the copper interconnects and the surrounding dielectric is required to avoid copper delamination. However, copper CMP is a destructive process to both the copper and the dielectric interface. Successive deposition of dielectric layers results in the formation of unstable copper surface and the creation of CuO residues resulting in the occurrence of surface bubbles and copper to dielectric delamination. The invention addresses these problems by providing a method of treating the copper surface and to remove the CuO from the surface of the copper to dielectric interface.
FIG. 1 gives an overview of the Prior Art Damascene process, as follows:
FIG. 1a shows the metal plug formed after the surface planarization. PA0 FIG. 1b shows the deposition of the Intra Level Dielectric. PA0 FIG. 1c shows the formation of the trenches for metal lines. PA0 FIG. 1d shows the deposition of metal to fill the trenches. PA0 FIG. 1e shows the removal of the excess metal on the surface.
The elements shown in FIGS. 1a though 1e are the following:
10 (FIG. 1a) is a damascene plug. PA1 14 (FIG. 1a) is a semiconductor layer in the surface of which a damascene plug is created. PA1 12(FIG. 1a) is the surface of layer 14 after layer 14 has been polished. PA1 16 (FIG. 1b) is a layer of intra metal dielectric that has been deposited over the surface of layer 14. PA1 18 (FIG. 1c) are the openings that are created in layer 16 of dielectric for damascene trenches. PA1 20 (FIG. 1d) is the layer of conductive material that is deposited over the exposed surface of layer 14, including the surface of the patterned layer 16 of dielectric. PA1 22 (FIG. 1e) are the conductive damascene interconnect lines overlying the damascene via 10. PA1 26 (FIG. 1e) is the surface of the layer 16 of dielectric and the damascene trenches 22 after the excess conductive material (20, FIG. 1d) has been removed from above the layer 16 of dielectric.
FIG. 2a gives and overview of the sequence of steps required of forming a Prior Art dual Damascene structure. The numbers referred to in the following description of the formation of the dual Damascene structure relate to the cross section of the completed dual Damascene structure that is shown in FIG. 2b.
FIG. 2a, 11 shows the creation of the bottom part of the dual Damascene structure by forming a via pattern 22 on a surface 24, this surface 24 can be a semiconductor wafer but is not limited to such. The via pattern 22 is created in the plane of a dielectric layer 20 and forms the lower part of the dual Damascene structure. SiO.sub.2 can be used for this dielectric.
FIG. 2a, 12 shows the deposition within plane 30 (FIG. 2b) of a layer of non-metallic material such as poly-silicon on top of the first dialectric 20 and across the vias 22, filling the via openings 22.
FIG. 2a, 13 shows the formation of the top section 41 of the dual Damascene structure by forming a pattern 41 within the plane of the non-metallic layer 30. This pattern 41 mates with the pattern of the previously formed vias 22 (FIG. 2a, 11) but it will be noted that the cross section of the pattern openings 41 within the plane 30 of the non-metallic layer is considerably larger than the cross section of the via openings 22 (FIG. 2a, 11). After pattern 41 has been created and as part of this pattern creation step, the remainder of the non-metallic layer 30 is removed, the pattern 41 remains at this time.
FIG. 2a, 14 shows the deposition and planarization (down to the top surface of pattern 41) of an inter level dielectric (ILD) 50, a poly-silicon can be used for this dielectric.
FIG. 2a, 15 shows the creation of an opening by removing the poly-silicon from the pattern 41 and the vias 22. It is apparent that this opening now has the shape of a T and that the sidewalls of the opening are not straight but show a top section that is larger than the bottom section.
FIG. 2a, 16 shows the cross section of the dual Damascene structure where a barrier 70 has been formed on the sides of the created opening. The opening, which has previously been created by removing the poly-silicon from the pattern 41 and the vias 22, has been filled with a metal. Metal such as Wolfram or copper can be used for this latter processing step.
U.S. Pat. No. 5,527,739 (Parrillo et al.) teaches a Cu layer with a Cu permeable or refractory metal (e.g. Ti) overlying and a forming gas anneal. However, this reference differs from the invention.
U.S. Pat. No. 5,807,660 (Lin et al.) shows a N.sub.2 O plasma treatment for an oxide layer to improve adhesion to photoresist.
U.S. Pat. No. 5,814,557 (Venkatraman et al.) teaches an Al cap over a Cu plug.
U.S. Pat. No. 5,731,245 (Joshi et al. hard cap. shows a Cu plug with a CuGe hard cap.
U.S. Pat. No. 5,612,254 (Mu et al.) shows a Cu interconnect with a SiN layer thereover.